In a semiconductor integrated circuit in which sequential logic circuits, such as flip-flop circuits, or registers, counters or the like having flip-flop circuits as the basic configuration, are used in the internal circuits, there is a fear of malfunction due to unsteady levels when the power is turned ON, so generally, the semiconductor integrated circuit contains a power-ON-clear circuit (for example, refer to Patent Document 1). By having this power-ON-clear circuit operate when the power is turned ON in order to reset or initialize the internal circuits, it is possible to prevent the semiconductor integrated circuit from malfunctioning.
A conventional power-ON-clear circuit will be explained below with reference to FIG. 5. The power-ON-clear circuit 10 comprises a resistor R11, capacitors C11, C12, N-channel MOS transistor Q11 and inverter INV11. The resistor R11 and capacitor C11 are connected in series between the power-supply voltage Vcc and the ground potential Gnd. The capacitor C12 and transistor Q11 are connected in series between the power-supply voltage Vcc and the ground potential Gnd, and the gate of the transistor Q11 is connected to the connecting point, or in other words, the node ND11 between the resistor R11 and capacitor C11. The input terminal of the inverter INV11 is connected to the connecting point, or in other words, the node ND12 between the capacitor C12 and the drain of the transistor Q11. The output signal from the inverter INV11 is output as a reset signal RES to the internal circuits (not shown in the figure) that are connected in a later stage.
In a power-ON-clear circuit 10 that is constructed in this way, after the power-supply voltage Vcc begins to be supplied, first, the node ND12 is pulled up by the capacitor C12 and maintained at nearly the power-supply voltage Vcc. At this time, the reset signal RES from the inverter INV11 is maintained at low level. The capacitor C11 is charged via the resistor R11, so the gate voltage of the transistor Q11 rises gradually, and when it reaches the threshold voltage of the transistor Q11, the transistor Q11 changes to the conductive state. In response to this, the node ND12 changes from high level to low level. Also, the reset signal RES from the inverter INV11 changes from low level to high level. When the reset signal RES is low level, the internal circuits that are connected in a later stage are reset, and when the reset signal RES becomes high level, the reset state is cleared.
Next, a semiconductor integrated circuit 100 that contains the power-ON-clear circuit 10 described above will be explained with reference to FIG. 6. In this semiconductor integrated circuit 100, when an internal circuit that is reset or initialized by the power-ON-clear circuit 10 comprises a transistor having a low breakdown voltage, and when the external power-supply voltage Vcc1 equals or is greater than that breakdown voltage, the output level of the power-ON-clear circuit 10 must be set to a voltage level that corresponds to the breakdown voltage of this transistor and that is lower than the external power-supply voltage Vcc1. As a means for accomplishing this, the semiconductor integrated circuit 100 contains a voltage regulator 20 that regulates the external power-supply voltage Vcc1 to an internal power-supply voltage Vcc2.
The voltage regulator 20 comprises an output P-channel MOS transistor Q21, a differential amplifier 21, a voltage-dividing circuit 22 comprising voltage-dividing resistors R21, R22, and a reference-voltage source 23. The MOS transistor Q21 and voltage-dividing circuit 22 are connected in series between the external power-supply voltage Vcc1 and ground potential Gnd, and the serial connecting point between them, or in other words, node ND21, is the output terminal of the internal power-supply voltage Vcc2. The serial connecting point between the voltage-dividing resistors R21, R22, or in other words, node ND22, is connected to the non-inverting input terminal of the differential amplifier 21. A reference-voltage supply 23 is connected to the inverting input terminal of the differential amplifier 21. The output terminal of the differential amplifier 21 is connected to the gate of the MOS transistor Q21. An ESD (Electro Static Discharge) protection diode D21 is connected between the external power-supply voltage Vcc1 and node ND21, and an ESD protection diode D22 is connected between node ND21 and the ground potential Gnd. Also, an external smoothing capacitor C1 is connected between node ND21 and the ground potential Gnd.
In the semiconductor integrated circuit 100, when the external power-supply voltage Vcc1, for example, Vcc1=3V is supplied to the voltage regulator 20, the voltage regulator 20 generates an internal power-supply voltage Vcc2, for example, Vcc2=2V, and this internal power-supply voltage Vcc2 is supplied from the voltage regulator 20 to the power-ON-clear circuit 10 instead of the external power-supply voltage Vcc1. At this time, as shown in FIG. 7, in the power-ON-clear circuit 10, there is a period (reset period) from time T1 to time T2 when the reset signal RES is low level.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2003-8426A (see FIG. 5)